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SH66P22A
OTP 4-bit Microcontroller
Features
SH6610C-based single-chip 4-bit micro-controller OTPROM: 4K X 16 bits RAM: 160 X 4 bits (data memory) Operation voltage: 2.4V - 6.0V (typical 3.0V or 5.0V) 22 CMOS bi-directional I/O pins 4-level subroutine nesting (including interrupts) One 8-bit auto re-load timer/counter Warm-up timer for power on reset Powerful interrupt sources: - Internal interrupt (Timer0) - External interrupts: PortB & PortC (falling edge) Oscillator (OTP option) - Xtal oscillator: 32.768KHz - 4MHz - Ceramic resonator: 400K - 4MHz - RC oscillator : 400K - 4MHz - External clock: 30K - 4MHz Instruction cycle time: - 4/32.768KHz(122us) for 32.768KHz OSC clock - 4/4MHz (1us) for 4MHz OSC clock Two low power operation modes: HALT and STOP Built-in watch dog timer (OTP option) Built-in power on reset
General Description
SH66P22A is a 4-bit micro controller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 4K OTPROM, Timer and I/O Ports.
Pin Configuration
PE2 PE3 PF1 PA2 PA3 T0 RESET GND PB0 PB1 PB2 PB3 PD0 PD1
1 2 3 4
28 27 26 25
PE1 PE0 PF0 PA1 PA0 OSCI OSCO VDD PC3 PC2 PC1 PC0 PD3 PD2
SH66P22A
5 6 7 8 9 10 11 12 13 14
24 23 22 21 20 19 18 17 16 15
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V2.4
SH66P22A
Block Diagram
RESET OSCO
OSCI
OSC WDTEN RC
CPU
Power on RESET
PRESCLALER
PORTA ( 4-BITS ) PORTA [0:3] PORTB ( 4-BITS ) PORTB [0:3]
WATCHDOG TIMER
T0
8-BITS TIMER ( Up counter )
PORTC ( 4-BITS ) CTL REG. PORTC [0:3] WDT TIMER OUT OTPROM 4096*16 BITS PORTE ( 4-BITS ) DATA RAM 160*4 BITS PORTF ( 2-BITS ) PORTF [0:1] PORTE [0:3] PORTD (4-BITS ) PORTD [0:3]
TIMER INTERRUPT
Pin Description
Pin No. 27, 28, 1, 2 26, 3 24, 25, 4, 5 6 7 8 9 - 12 13- 16 17 - 20 21 22 23 Designation PE.0 - PE.3 PF.0 - PF.1 PA.0 - PA.3 T0 RESET GND PB.0 - PB.3 PD.0 - PD.3 PC.0 - PC.3 VDD OSCO OSCI I/O I/O I/O I/O I I P I/O I/O I/O P O I Bit programmable I/O Bit programmable I/O Bit programmable I/O Timer Clock/Counter input pin. (Schmitt trigger input) Reset input (active low, Schmitt trigger input) Ground pin Bit programmable I/O. Vector Interrupt (active falling edge) Bit programmable I/O Bit programmable I/O. Vector Interrupt (active falling edge) Power supply pin OSC output pin. Output a frequency of Fosc/4 for RC mode OSC input pin, connected to a crystal, ceramic or external resistor Descriptions
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SH66P22A
Function Description
1. CPU The CPU contains the following function blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, and DPL), and the Stack. 1.1. PC (Program Counter) The Program Counter is used to address the 4K program ROM. It consists of 12-bits: the Page Register (PC11), and the Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). The program counter normally increases by one (+1) with every execution of an instruction except in the following cases: (1) When executing a jump instruction (such as JMP, BA0, BAC), (2) When executing a subroutine call instruction (CALL), (3) When an interrupt occurs, (4) When the chip is in the INITIAL RESET mode. The program counter is loaded with data corresponding to each instruction. The unconditional jump instruction (JMP) can be set at 1-bit page register for higher than 2K. 1.2. ALU and CY ALU performs arithmetic and logic operations. The ALU provides the following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustment for addition/subtraction (DAA, DAS) Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) Decision (BA0, BA1, BA2, BA3, BAZ, BAC) Logic Shift (SHR) The Carry Flag (CY) holds the ALU overflow which the arithmetic operation generates. During an interrupt servicing or call instruction, the carry flag is pushed into the stack and retrieved back from the stack by the RTNI instruction. It is unaffected by the RTNW instruction. 1.3. Accumulator The Accumulator is a 4-bit register holding the results of the arithmetic logic unit. In conjunction with the ALU, data transfer between the accumulator and system register or data memory can be performed. 1.4. Stack A group of registers are used to save the contents of CY & PC (10-0) sequentially with each subroutine call or interrupt. It is organized into 13 bits X 4 levels. The MSB is saved for CY. 4 levels are the maximum allowed for subroutine calls and interrupts. The contents of the Stack are returned sequentially to the PC with the return instructions (RTNI/RTNW). The stack is operated on a first-in, last-out basis. This 4-level nesting includes both subroutine calls and interrupts requests. Note that program execution may enter an abnormal state if the number of calls and interrupt requests exceed 4, and the bottom of the stack will be shifted out.
2. OTPROM The SH66P22A can address up to 4096 X 16 bit words of program area from $000 to $FFF. Service routine as starting vector address. Address $000H $001H $002H $003H $004H Instruction JMP Instruction NOP JMP Instruction NOP JMP Instruction Remarks Jump to RESET service routine Reserved Jump to TIMER0 service routine Reserved Jump to PBC service routine
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SH66P22A
3. RAM The built-in RAM consists of general-purpose data memory and the system register. Direct addressing in one instruction can access both data memory and the system register. The following is the memory allocation map: $000 - $01F: System register and I/O. $020 - $0BF: Data memory (160 X 4 bits, divided into 2 banks. $020 - $07F: bank0, $080 - $0BF: bank1). The Configuration of the System Register Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 - $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F Bit3 TL0.3 TH0.3 LPD3 PA.3 PB.3 PC.3 PD.3 PE.3 TBR.3 INX.3 DPL.3 Bit2 IET0 IRQT0 TM0.2 TL0.2 TH0.2 LPD2 PA.2 PB.2 PC.2 PD.2 PE.2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 PA3OUT PB3OUT PC3OUT PD3OUT PE3OUT WDT PA2OUT PB2OUT PC2OUT PD2OUT PE2OUT Bit1 TM0.1 TL0.1 TH0.1 LPD1 PA.1 PB.1 PC.1 PD.1 PE.1 PF.1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 PA1OUT PB1OUT PC1OUT PD1OUT PE1OUT PF1OUT T0S Bit0 IEP IRQP TM0.0 TL0.0 TH0.0 LPD0 PA.0 PB.0 PC.0 PD.0 PE.0 PF.0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 PA0OUT PB0OUT PC0OUT PD0OUT PE0OUT PF0OUT T0E R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W W W W W Remarks Interrupt enable flags Interrupt request flags Timer0 Mode register (Prescaler) Reserved Timer0 load/counter register low digit Timer0 load/counter register high digit Reserved LPD Enable Control (LPD3 - 0): 1010: LPD Enabled (Default); 0101: LPD Disabled PORTA PORTB PORTC PORTD PORTE PORTF Table Branch Register Pseudo index register Data pointer for INX low nibble Data pointer for INX middle nibble Data pointer for INX high nibble Reserved Set PORTA as an output port Set PORTB as an output port Set PORTC as an output port Set PORTD as an output port Set PORTE as an output port Set PORTF as an output port Bit0: T0 signal edge; Bit1: T0 signal source Reserved Bit3: Watchdog timer reset (write 1 to reset WDT) Reserved
* System Register $00 - $12 (except $07H) refer to "SH6610C User manual".
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SH66P22A
Low Power Detection (LPD) The LPD function is used to monitor the supply voltage and applies an internal reset in the micro-controller at the time of battery replacement. If the applied circuit satisfies the following conditions, the LPD can be incorporated using software control. - High reliability is not required - Power supply voltage VDD = 2.4 to 6.0 V - Operating ambient temperature TA = -10 to + 60 Functions of the LPD Circuit The LPD circuit has the following functions: - It generates an internal reset signal when VDD VLPD - It cancels the internal reset signal when VDD > VLPD Here, VDD: power supply voltage, VLPD: LPD detect voltage, about 1.6 - 1.7V and lower than VDD-MIN (2.4V) LPD Control Register The LPD circuit is controlled by the software enable flag Address $07 Bit3 LPD3 Bit2 LPD2 Bit1 LPD1 Bit0 LPD0 R/W W Remark LPD Enable Control (LPD3 - 0): 1010: LPD Enable (Default); 0101: LPD Disable
LPD3 LPD2 LPD1 LPD0: 1 0 0 1 1 0 0 1
LPD Enable/Disable flag Enable LPD circuit (Power-on initial) Disable LPD circuit
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SH66P22A
System Register $16 - $1B Address $16 $17 $18 $19 $1A $1B Bit3 PA3OUT PB3OUT PC3OUT PD3OUT PE3OUT Bit2 PA2OUT PB2OUT PC2OUT PD2OUT PE2OUT Bit1 PA1OUT PB1OUT PC1OUT PD1OUT PE1OUT PF1OUT Bit0 PA0OUT PB0OUT PC0OUT PD0OUT PE0OUT PF0OUT R/W W W W W W W Remarks Set PORTA as an output port Set PORTB as an output port Set PORTC as an output port Set PORTD as an output port Set PORTE as an output port Set PORTF as an output port
Equivalent Circuit for a Single I/O Pin
VDD
DATA
D DATA
Q
AND
WRITE
CK
SET
QB
RESET
DATA IN READ CONTROL D PXXOUT WRITE CK RESET QB OR Q
I/O PIN
RESET
GND
PAXOUT, PBXOUT, PCXOUT, PDXOUT, PEXOUT (X = 0, 1, 2, 3), PFXOUT (X = 0, 1) 1: Use as an output buffer 0: Use as an input buffer (Power on initial) T0 & WDT System Register $1C Address $1C BIT3 BIT2 BIT1 T0S BIT0 T0E R/W W Remark Bit0: T0 signal edge Bit1: T0 signal source
T0E: T0 signal edge 0: Increment on low-to-high transition T0 pin (Power on initial) 1: Increment on high-to-low transition T0 pin T0S: T0 signal source. 0: OSC 1/4 (Power on initial). 1: Transition on T0 pin.
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SH66P22A
T0S OSC/4 0 M U X TIMER0 (8bits)
T0 TOE EOR
1
3 Built-in RC Oscillator TM0 [2:0] WDT Enable (OTP option ) WDT reset
WDT & Warm Up Counter
3
WDT Timeout
System Register $1E Address $1E Bit3 WDT Bit2 Bit1 Bit0 R/W W Remark Bit3: Watchdog timer reset. (write 1 to reset WDT)
The input clock of the watchdog timer is generated by a built-in RC oscillator so that the WDT will always run even in the STOP mode. SH66P22A generates a RESET condition when the watchdog times-out. The watchdog can be enabled or disabled permanently by using the OTP option. To prevent it timing out and generating a device RESET condition, you should write this bit as "1" before timing-out. The WDT has a time-out period of more than 7ms.If longer time-out periods are desired, a prescaler with a division ratio of up to 1:2048 can be assigned to the WDT under software controll by writing to the TM0 register. Prescaler divide ratio: TM0.2 1 1 1 1 0 0 0 0 TM0.1 1 1 0 0 1 1 0 0 TM0.0 1 0 1 0 1 0 1 0 Prescaler Divide Ratio 1:1 1:2 1:4 1:8 1:32 1:128 1:512 1:2048 (Power on initial) Timer-out Period 7ms 14ms 28ms 56ms 224ms 896ms 3,584ms 14,336ms
2.25ms RC OSC
Internal
SCALER_1
/8
WDT Time out Period 18ms
WDT PRESCALER TM0
/1
/2
/4
/8
/32 /128
/512
/2048
Final WDT Time out period
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SH66P22A
4. Timer0 SH66P22A has one 8-bit timer. The time/counter has the following features: . 8-bit timer/counter . Readable and writeable . Automatic reloadable counter . 8-prescaler scale is available . Internal and external clock select . Interrupt on overflow from $FF to $00 . Edge select for external event Following is a simplified timer block diagram:
Fosc/4 PRE-SCALER T0 T0M T0E T0C 8-BIT COUNTER
T0S
4.1. Configuration and Operation Timer0 consists of an 8-bit write-only timer load register (TL0L, TL0H), and an 8-bit read-only timer counter (TC0L, TC0H). The counter and load register both have low order digits and high order digits. Writing data into the timer load register (TL0L, TL0H) can initialize the timer counter. Load register programming: Write the low-order digit first and then the high-order digit. The timer counter is loaded with the contents of the load register automatically when the high order digit is written or the counter counts overflow from $FF to $00. Timer Load Register: Since the register H controls the physical READ and WRITE operation, please follow these rules: Write Operation: First write Low nibble, Then write High nibble to update the counter.
Read Operation: High nibble first; Followed by Low nibble.
Load Reg. L
Load Reg. H
8-bit timer counter Latch Reg. L
4.2. Timer0 Interrupt The timer overflow will generate an internal interrupt request, when the counter counts overflow from $FF to $00. If the interrupt enable flag is enabled, then a timer interrupt service routine will proceed. This can also be used to waken the CPU from HALT mode.
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SH66P22A
4.3. Timer0 Mode Register The timer can be programmed in several different prescaler ratios by setting the Timer Mode register (TM0). The 8-bit counter counts prescaler overflow output pulses. The timer mode registers (TM0) are 3-bit registers used for timer control as shown in table1. These mode registers select the input pulse sources into the timer. Table 1. Timer 0 Mode Register ($02) TM0.2 0 0 0 0 1 1 1 1 TM0.1 0 0 1 1 0 0 1 1 TM0.0 0 1 0 1 0 1 0 1 Prescaler Divide Ratio /2
11 9 7 5 3 4 1 0
Ratio N 2048 (initial) 512 128 32 8 4 2 1
/2 /2 /2 /2 /2 /2 /2
4.4. External Clock/Event T0 as Timer0 Source When an external clock/event input is used for the TM0, it is synchronized with the CPU system clock. Therefor the external source must follow certain constraints. The output from the T0M multiplex is T0C. It is sampled by the system clock in instruction frame cycle. Therefore it is necessary for the T0C to be high (at least 2 tOSC) and low (at least 2 tOSC). When the prescaler ratio 0 selects /2 , the T0C is the same as the system clock input. Therefore the requirement is as follows T0H = T0CH = T0 high time 2 tOSC + T T0L = T0CL = T0 low time 2 tOSC + T Note: T = 40ns When another prescaler ratio is selected, the TM0 is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical. Then: T0C high time = T0C low time = Where T0 = Timer0 input period N = prescaler value The requirement is, therefore:
4 * t OSC + 2 T N * T0 2 tOSC + T , or T0 N 2
N * T0 2
The limitation is applied for the T0 period time only. The pulse width is not limited by this equation. It is summarized as follows: T0 = Timer0 period
4 * t OSC + 2T N
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SH66P22A
5. Port Interrupt The PBC interrupt (PORTB & PORTC, 8bits) is falling edge active. This means that if an interrupt request (IEx is set to 1 and one port bit goes from high to low) is been touched, then the condition is the other port bits are high level. Only input port bits could cause interrupt. 6. System Clock and Oscillator System clock generator produces the basic clock pulses that provide the system clock to the CPU and any peripherals. Instruction cycle time (1) 4/32.768KHz (122us) for 32.768KHz system clock (2) 4/4MHz (1us) for 4MHz system clock Oscillator (1) Crystal oscillator: 32.768KHz - 4MHz.
OSCI C1 C1, C2 Setting : Crystal 32.768K - 4MHz OSCO C2
Crystal 32.768KHz : Typical: C1 = 20p C2 = 20p Crystal 4MHz : Typical: C1 = 10p C2 = 10p
(2) Ceramic resonator: 400KHz - 4MHz.
C1 OSCI C1, C2 Setting : Ceramic 400K - 4MHz
Ceramic 400KHz : Typical: C1 = 20p C2 = 20p Ceramic 4MHz : Typical: C1 = 10p C2 = 10p
OSCO C2
(3) RC oscillator: 400KHz - 4MHz.
VDD R OSCI OSCO Fosc/4
C1 = 1000p
(4) External input clock: 30KHz - 4MHz.
OSCI
External clock source
OSCO
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SH66P22A
Initial State
Hardware Program counter CY Data memory System register AC Pseudo index register DPL, DPM, DPH Table Branch Register Interrupt enable flag register Interrupt request flag register Timer mode register Timer counter Timer load register WDT counter WDT prescaler I/O ports LPD3 - 0 After Power on Reset $000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 0 0 0 0 0 0 Input 1010 (Enable LPD)
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SH66P22A
Instruction Set
All instructions are one cycle and one-word instructions. The characteristic is memory-oriented operation. Arithmetic and Logical Instruction Accumulator Type Mnemonic ADC ADCM ADD ADDM SBC SBCM SUB SUBM EOR EORM OR ORM AND ANDM SHR Immediate Type Mnemonic ADI ADIM SBI SBIM EORIM ORIM ANDIM X, I X, I X, I X, I X, I X, I X, I Instruction Code 01000 iiii xxx xxxx 01001 iiii xxx xxxx 01010 iiii xxx xxxx 01011 iiii xxx xxxx 01100 iiii xxx xxxx 01101 iiii xxx xxxx 01110 iiii xxx xxxx AC Function Mx + I Flag Change CY CY CY CY X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) Instruction Code 00000 0bbb xxx xxxx 00000 1bbb xxx xxxx 00001 0bbb xxx xxxx 00001 1bbb xxx xxxx 00010 0bbb xxx xxxx 00010 1bbb xxx xxxx 00011 0bbb xxx xxxx 00011 1bbb xxx xxxx 00100 0bbb xxx xxxx 00100 1bbb xxx xxxx 00101 0bbb xxx xxxx 00101 1bbb xxx xxxx 00110 0bbb xxx xxxx 00110 1bbb xxx xxxx 11110 0000 000 0000 AC Function Mx + AC + CY Flag Change CY CY CY CY CY CY CY CY
AC, Mx Mx + AC + CY AC Mx + AC
AC, Mx Mx + AC AC Mx + -AC + CY
AC, Mx Mx + -AC + CY AC Mx + -AC + 1
AC, Mx Mx + -AC + 1 AC Mx AC
AC, Mx Mx AC AC Mx | AC
AC, Mx Mx | AC AC Mx & AC
AC, Mx Mx & AC 0 AC[3]; AC[0] CY; AC shift right one bit CY
AC, Mx Mx + I AC Mx + -I +1
AC, Mx Mx + -I + 1 AC, Mx Mx I AC, Mx Mx | I AC, Mx Mx & I
* In the assembler ASM66 V1.0, the EORIM mnemonic is EORI. However, EORI has the identical operation to EORIM. The same is true for the ORIM with respect to ORI, and ANDIM with respect to ANDI. Decimal Adjustment Mnemonic DAA X DAS X Instruction Code 11001 0110 xxx xxxx 11001 1010 xxx xxxx Function AC; Mx Decimal adjustment for add. AC; Mx Decimal adjustment for sub. Flag Change CY CY
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SH66P22A
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SH66P22A
Transfer Instructions Mnemonic LDA STA LDI X (, B) X (, B) X, I Instruction Code 00111 0bbb xxx xxxx 00111 1bbb xxx xxxx 01111 iiii xxx xxxx AC Mx Mx AC Function Flag Change
AC, Mx I
Control Instructions Mnemonic BAZ X BNZ X BC X BNC X BA0 X BA1 X BA2 X BA3 X CALL X Instruction Code 10010 xxxx xxx xxxx 10000 xxxx xxx xxxx 10011 xxxx xxx xxxx 10001 xxxx xxx xxxx 10100 xxxx xxx xxxx 10101 xxxx xxx xxxx 10110 xxxx xxx xxxx 10111 xxxx xxx xxxx 11000 xxxx xxx xxxx PC PC PC PC PC PC PC PC ST PC PC AC Function X if AC = 0 X if AC 0 X if CY = 1 X if CY 1 X if AC(0) = 1 X if AC(1) = 1 X if AC(2) = 1 X if AC(3) = 1 CY; PC + 1 X (Not including p) ST; TBR hhhh; llll CY Flag Change
RTNW H, L RTNI HALT STOP JMP X TJMP NOP Where, PC AC -AC CY Mx p ST
11010 000h hhh llll 11010 1000 000 0000 11011 0000 000 0000 11011 1000 000 0000 1110p xxxx xxx xxxx 11110 1111 111 1111 11111 1111 111 1111
CY; PC ST
PC PC
X (Including p) (PC11-PC8) (TBR) (AC)
No Operation
Program counter Accumulator Complement of accumulator Carry flag Data memory ROM page Stack
I | & bbb B TBR
Immediate data Logical exclusive OR Logical OR Logical AND RAM bank RAM bank. Every $7F as one RAM bank. Table Branch Register
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SH66P22A
Absolute Maximum Rating*
DC Supply Voltage . . . . . . . . . . . . . . -0.3V to + 7.0V Input Voltage . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Operating Ambient Temperature . . . -10 to + 60 Storage Temperature . . . . . . . . . . .-55 to + 125
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VDD = 5.0V GND = 0V, TA = 25, FOSC = 4MHz, unless otherwise specified) Parameter Operating Voltage Operating Current Stand by Current (HALT) Stand by Current (STOP) Input Low Voltage Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Symbol VDD IOP ISB1 ISB2 VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 IIL1 IIL2 IIL3 IIL4 IIL5 VOH VOL -3 -3 VDD - 0.7 GND GND GND 0.8 X VDD 0.85 X VDD 0.85 X VDD -1 -5 1 1 1 5 3 3 GND + 0.6 1 Min. 4.5 1 Typ. Max. 6 2 0.5 2 0.2 X VDD 0.15 X VDD 0.15 X VDD VDD VDD VDD 1 Unit V mA mA A V V V V V V A A A A A V V All output pins unloaded (Execute NOP instruction) All output pins unloaded Condition
All output pins unloaded,
LPD off (If LPD on, ISB2X = ISB2 + 3A) WDT off (If WDT on, ISB2X = ISB2 + 15A) I/O ports, pins tri-state
RESET , T0
OSCI (Driven by external clock) I/O ports, pins tri-state
RESET , T0
OSCI (Driven by external Clock) I/O ports, GND < VI/O < VDD V RESET = GND + 0.25V V RESET = VDD T0, GND < Vt0 < VDD For OSCI I/O ports, IOH = -10mA, OSCORC, IOH = -0.7mA I/O ports, IOL = 20mA, OSCORC, IOL = 1.6mA
AC Electrical Characteristics (VDD = 5.0V GND = 0V, TA = 25, unless otherwise specified) Parameter Oscillator Start Time Oscillator Start Time Oscillator Start Time Oscillator Start Time WDT Period Frequency Stability (crystal) Frequency Variation (crystal) Frequency Stability (ceramic) Frequency Variation (RC) Frequency Stability (RC) Symbol Min. Typ. Max. Unit TOSC1 TOSC2 TOSC3 TOSC4 TWDT F/F F/F F/F F/F F/F 1 20 2 2 7 18 1 10 0.1 20 5 s ms ms ms ms ppm ppm % % % Condition X'tal osc = 32.768KHz Ceramic osc = 400KHz RC Osc = 400KHz RC Osc = 4MHz VDD = 5.0V Crystal Oscillator: [F(5.0)-F(4.5)]/F(5.0) Crystal Oscillator: C1 = C2 = 5 - 30p Ceramic Resonator Osc: [F(5.0)-F(4.5)]/F(5.0) Include supply voltage and chip to chip variation RC Oscillator: [F(5.0)-F(4.5)]/F(5.0)
User Notice: Max. Current into VDD = 50mA; Max. Current out of VSS = 150mA Max. Output current sunk by any I/O port = 25mA;
Max. Output current sourced by any I/O port = 20mA Max. Output current sunk by all ports (A, B, C, D, E, F) = 50mA; Max. Output current sourced by all ports (A, B, C, D, E, F) = 40mA
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SH66P22A
DC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25, FOSC = 4MHz, unless otherwise specified) Parameter Operating Voltage Operating Current Stand by Current (HALT) Stand by Current (STOP) Input Low Voltage Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Symbol VDD IOP ISB1 ISB2 VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 IIL1 IIL2 IIL3 IIL4 IIL5 VOH VOL -3 -3 VDD - 0.7 GND + 0.4 GND GND GND 0.8 X VDD 0.85 X VDD 0.85 X VDD -1 -5 1 1 1 5 3 3 1 Min. 2.4 0.7 Typ . Max. 4.5 1.3 0.2 2 0.2 X VDD 0.15 X VDD 0.15 X VDD VDD VDD VDD 1 Unit V mA mA A V V V V V V A A A A A V V All output pins unloaded (Execute NOP instruction) All output pins unloaded Condition
All output pins unloaded,
LPD off (If LPD on, ISB2X = ISB2 + 3A) WDT off (If WDT on, ISB2X = ISB2 + 5A) I/O ports, pins tri-state RESET , T0 OSCI (Driven by external clock) I/O ports, pins tri-state RESET , T0 OSCI (Driven by external Clock) I/O ports, GND < Vi/o < VDD V RESET = GND + 0.25V V RESET = VDD T0, GND < Vt0 < VDD For OSCI I/O ports, IOH = -7mA, VDD = 3V OSCORC, IOH = -0.7mA, VDD = 3V I/O ports, IOL = 8mA, VDD = 3V OSCORC, IOL = 1.0mA, VDD = 3V
AC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25, unless otherwise specified) Parameter Oscillator Start Time Oscillator Start Time Oscillator Start Time WDT Period Frequency Stability (crystal) Frequency Variation (crystal) Frequency Stability (ceramic) Frequency Variation (RC) Frequency Stability (RC) Symbol TOSC1 TOSC2 TOSC3 TWDT F/F F/F F/F F/F F/F 7 18 1 10 0.1 20 5 Min. Typ. Max. 1 35 5 Unit s ms ms ms Condition Crystal Osc = 32.768KHz, VDD = 3.0V Ceramic Osc = 400KHz, VDD = 3.0V RC Osc = 400KHz, VDD = 3.0V VDD = 3.0V
PPM Crystal oscillator: [F(3.0)-F(2.7)]/F(3.0) PPM Crystal oscillator: C1 = C2 = 5 - 30P % % % Ceramic resonator OSC:[F(3.0)-F(2.7)]/F(3.0) Include supply voltage and chip to chip variation RC oscillator (1MHz): [F(3.0)-F(2.7)]/F(3.0)
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SH66P22A
AC Characteristics Symbol TCY TIW TIWH TIWL Parameter Instruction Cycle Time T0 Input Width High Pulse Width LOW Pulse Width Min. 1 (TCY + 40)/N 1/2 tIW 1/2 tIW Typ. Max. 122 Unit s ns ns ns N = Prescaler divide ratio Condition
Timing Waveform
T0 Input Waveform
TiwH
TiwL
T0 Tiw
RC OSCO Timing Waveform
0ns RC - OSC PORT OSCO - RC
1000ns
T1 T2 T3 T4 T5 T6 T7 T8 T1 T2 T3 T4 T5 T6
17
SH66P22A
Typical RC oscillator Resistor vs. Frequency: (VDD = 5V, for reference only)
10000
F (KHz)
1000
100
0 200 400 600 800 1000 1200 1400 1600 1800
R (K)
Typical RC Oscillator Resistor vs. Frequency: (VDD = 3V, for reference only)
10000
F (KHz)
1000
100
0 200 400 600 800 1000 1200 1400 1600 1800
R (K)
18
SH66P22A
Application Circuit (for reference only)
AP1 (1) Operating voltage: 5.0V (2) Oscillator: Ceramic resonator 400KHz (3) T0 input timer clock / counter (4) PORTA - F: I/O
T0 VDD 47K
OSCI
SH66P22A
OSCO PORTA ~ PORTF
20P
C1 GND
I/O
AP2 (1) Operating voltage: 5.0V. (2) Oscillator: RC 400KHz. (3) PORTA - E: I/O
VDD 47K 22K T0 OSCI
SH66P22A
OSCO PORTA ~ PORTF
1000PF
C1
RESET
GND
I/O
19
SH66P22A
AP3 (1) PORTA - C: as scan KEY BOARD (32 keys) (2) PORTD - F: I/O
Pull-high resistor 47K
VDD
I/O
PORTD ~ PORTF
SH66P22A
PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PA0 PA1 PA2 PA3
20
SH66P22A
Ap4 (Weight Scale) (1) Operating voltage: 5.0V (2) Oscillator: Ceramic resonator 4MHz (3) Port A0: External interrupt input for ON/OFF switch (4) Port E2, E3, F1, A2: S4 - S1 analog switch control signals that control Vil is being charged or discharged by both the reference voltage (Vref) and the amplified voltage (Vo). The charging and discharging times are determined by the values of C1, R4 and the threshold voltage of the T0 input pin and the ADC resolution can be up to 8 bit (5) Other Ports: Sink seven-segment LED current directly. 0 - 199 can be displayed in this configuration
VDD VDD Vref R2 R3 Vi R1 R2 R3 R4 Vo
S3
Load Cell
R5
S1 S2 ON/OFF
Vi1 1 S1 PE2 2 S2 PE3 3 S3 PF1 4 S4 PA2 5 6 PA3 7 T0 8 RESET GND 9 PB0 10 PB1 11 PB2 12 PB3 13 PD0 14 PD1 PE1 PE0 PF0 PA1 PA0 OSCI OSCO VDD PC3 PC2 PC1 PC0 28 27 26 25 24 23 22 21 VDD 20 19 18 17 16 PD3 15 PD2
C1 Instrumentation Amplifier R6
S4 100
C 1 4MHz 2 120P - 470P XC1 C 120P - 470P
Vo = (1 + 2R2/R1) (R4/R3)Vi
47K
0.1u
abc de f g
abc de f g
abc de f g
21
SH66P22A
AP5: Reset Protection Circuit 1
VDD
SH66P22A
33K 10K
RESET
40K
RESET will be pulled to GND when VDD goes lower than Zener voltage + 0.7V. AP6: Reset Protection Circuit 2
VDD R1
SH66P22A
10K RESET R2 40K
RESET will be pulled to GND when (VDD X R1/(R1 + R2)) is lower than 0.7V
22
SH66P22A
Bonding Diagram
T 0
P A 3
P A 2
P F 1
G N D
P E 3
P E 2
P E 1
P E 0
P F 0
P A 1
P A 0
6
5
4
3
2
1
28
27
26
25
24 23
OSCI
RESET
7 8 22
OSCO GND3
GND1
SH66P22A
21 20 9
P B 0
VDD PC3
10
P B 1
11
P B 2
12
P B 3 G N D 2
13
P D 0
14
P D 1
15
P D 2
16
P D 3
17
P C 0
18
P C 1
19
P C 2
NOTE: 1. GND1, GND2&GND3 BONDING TO GROUND. 2. SUBSTRATE CONNECT TO GROUND.
unit: m Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Designation PE 2 PE 3 GND1 PF 1 PA 2 PA 3 T0
RESET
X 63.00 -67.00 -199.70 -332.40 -462.40 -592.40 -752.95 -818.85 -818.15 -792.15 -662.15 -532.15 -402.15 -269.45 -136.75 -6.75
Y 725.35 725.35 725.35 725.35 725.35 725.35 725.35 481.85 350.90 -725.30 -725.30 -725.30 -725.30 -725.30 -725.30 -725.30
Pad No 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Designation PD 2 PD 3 PC 0 PC 1 PC 2 PC 3 VDD GND3 OSCO OSCI PA 0 PA 1 PF 0 PE 0 PE 1
X 123.25 253.25 386.95 516.95 646.95 775.80 780.55 771.05 780.55 780.55 716.70 586.70 456.70 323.00 193.00
Y -725.30 -725.30 -725.30 -725.30 -725.30 -506.95 -328.00 -196.60 -65.65 462.60 725.35 725.35 725.35 725.35 725.35
GND PB 0 PB 1 PB 2 PB 3 GND2 PD 0 PD 1
23
SH66P22A
Ordering Information
Part No. SH66P22AH-yyxxx/000HR SH66P22AK-yyxxx/028KU SH66P22AM-yyxxx/028MU SH66P22A-yyxxx/028DU Package Chip Form 28L SKINNY 28L SOP 28L DIP Packing Tray Tube Tube Tube
Note: (1) "-yyxxx": "yy" means 2 bits option and "xxx" means 3 bits code seriary number. If the product is OTP type and in blank order, those bits should be none. (2) The data after mark "/" in Part No. block is the package and packing information for ordering. (3) The size of those package types are showed in "Package Information" (Page24 - Page26). (4) Any other package or packing request, please refer to following table. Package D F H J K L M N Q S T V W X DIP QFP CHIP CER-DIP SKINNY PLCC SOP OTHER GOOD DIE ON WAFER SOJ TO92 VSOP/TSOP WAFER TSSOP R U A D L B T S N Packing Normal package size and in tray packing Normal package size and in tube packing Normal package size and in tape & reel packing Larger package size and in tray packing Larger package size and in tube packing Larger package size and in tape & reel packing Smaller package size and in tray packing Smaller package size and in tube packing Smaller package size and in tape & reel packing
24
SH66P22A
Package Information
SKINNY_28L Outline Dimensions unit: inches/mm
D 28 15
E1
1 S
14 E C
A2
A1
A
Base Plane
L
Mounting Plane B e1 B1 eA
Symbol A A1 A2 B B1 C D E E1 e1 L eA S
Dimensions in inches 0.175 Max. 0.010 Min. 0.130 0.005 0.018 +0.004 -0.002 0.060 +0.004 -0.002 0.010 +0.004 -0.002 1.388 Typ. (1.400 Max.) 0.310 0.010 0.288 0.005 0.100 0.010 0.130 0.010 0 ~ 15 0.350 0.020 0.055 Max.
Dimensions in mm 4.45 Max. 0.25 Min. 3.30 0.13 0.46 +0.10 -0.05 1.52 +0.10 -0.05 0.25 +0.10 -0.05 35.26 Typ. (35.56 Max.) 7.87 0.25 7.32 0.13 2.54 0.25 3.30 0.25 0 ~ 15 8.89 0.51 1.40 Max.
Notes: 1. The maximum value of dimension D includes the end flash. 2. Dimension E1 does not include the resin fins. 3. Dimension S includes the end flash.
25
SH66P22A
SOP 28L Outline Dimensions unit: inches/mm
28
15 e1 ~ ~
HE
E
L 1 D b 14
Detail F
e1 c A2 A
s Seating Plane
e
y D
A1
LE See Detail F
Symbol A A1 A2 b c D E e e1 HE L LE S y
Dimensions in inches 0.110 Max. 0.004 Min. 0.093 0.005 0.016 +0.004 -0.002 0.010 +0.004 -0.002 0.705 0.020 0.295 0.010 0.050 0.006 0.376 NOM. 0.406 0.012 0.036 0.008 0.055 0.008 0.043 Max. 0.004 Max. 0 ~ 10
Dimensions in mm 2.79 Max. 0.10 Min. 2.36 0.13 0.41 +0.10 -0.05 0.25 +0.10 -0.05 17.91 0.51 7.49 0.25 1.27 0.15 9.40 NOM. 10.31 0.31 0.91 0.20 1.40 0.20 1.09 Max. 0.10 Max. 0 ~ 10
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
26
SH66P22A
DIP 28L Outline Dimensions unit: inches/mm
D 28 15
E1
1 S
14 E C
A2
A
A1
Base Plane Seating Plane B B1 e1 eA
L
Symbol A A1 A2 B B1 C D E E1 e1 L eA S
Dimensions in inches 0.210 Max. 0.010 Min. 0.155 0.010 0.018 +0.004 -0.002 0.060 +0.004 -0.002 0.010 +0.004 -0.002 1.460 Typ. (1.480 Max.) 0.600 0.010 0.550 Typ. (0.562 Max.) 0.100 0.010 0.130 0.010 0 ~ 15 0.655 0.035 0.090 Max.
Dimensions in mm 5.33 Max. 0.25 Min. 3.94 0.25 0.46 +0.10 -0.05 1.52 +0.10 -0.05 0.25 +0.10 -0.05 37.08 Typ. (37.59 Max.) 15.24 0.25 13.97 Typ. (14.27 Max.) 2.54 0.25 3.30 0.25 0 ~ 15 16.64 0.89 2.29 Max.
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash.
27
SH66P22A
Data Sheet Revision History
Version 2.4 2.3 2.2 2.1 2.0 1.0 Add P-DIP 28L package Change RC Frequency Variation to 20% Add Reset Protection Circuit (AP5 and AP6) Change SOP (W.B.) 28L package to SOP (N.B.) 28L package Original Content Add package and packing information in ordering information Date Jul.2004 Oct. 2002 Apr. 2002 Dec. 2001 Nov. 2001 Jul. 2000
28

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